1. Field of the Invention
The present invention relates to systems and techniques for determining a full-field Mask Error Enhancement Function associated with photo-masks for use in photo-lithography.
2. Related Art
Photo-lithography is a widely used technology for producing integrated circuits. In this technique, a light source illuminates a photo-mask. The resulting spatially varying light pattern is projected onto a photoresist layer on a semiconductor wafer by an optical system (referred to as an exposure tool). By developing the 3-dimensional pattern produced in this photoresist layer, a layer in the integrated circuit is created. Furthermore, because there are often multiple layers in a typical integrated circuit, these operations may be repeated using several photo-masks to produce a product wafer.
As dimensions in integrated circuits steadily become a smaller fraction of the wavelength of the light used to expose images of the photo-mask onto the wafer (which corresponds to a low k1 factor in the photo-lithographic process), it is becoming increasingly difficult to design and manufacture photo-masks that produce the desired target wafer pattern on the wafer. As a consequence, the structures in or on the ideal photo-mask (also referred to as the target mask pattern) and/or the physical structures in or on the actual photo-mask bear less and less resemblance to the desired target wafer pattern. These differences between the photo-mask and the target wafer pattern (which are sometimes referred to as ‘resolution enhancement technology’ or RET) are used to compensate for the diffraction and optical-proximity effects that occur when light is transmitted through the optics of the exposure tool and is converted into the 3-dimensional pattern in the photoresist.
When designing photo-masks for use in the low k1-factor regime, the manufacturing performance of a given RET solution is often evaluated in photo-lithography simulations based on the process window, which determines how sensitive the photo-lithographic process is to manufacturing process variations. Note that the process window can be characterized by its depth of focus (DOF) at a given exposure latitude (EL).
Traditionally, the process-window calculation assumes a perfect photo-mask, with no photo-mask errors or corner rounding. However, in the low k1-factor regime the consequences of photo-mask errors for the resulting wafer pattern (which are often measured using the Mask Error Enhancement Factor or MEEF) are large enough that photo-mask errors can no longer be ignored when calculating the process-window. Consequently, a limited number of MEEF values are typically calculated based on critical-dimension (CD) changes across cutlines that are associated with photo-mask errors.
Unfortunately, the extensive use of RET in the low k1-factor regime significantly increases the complexity of the two-dimensional photo-lithography simulations because of strong optical-proximity effects among neighboring features and the strong correlations between the illumination conditions, the photo-mask and the RET solution. As a consequence, analyzing and characterizing the MEEF using the traditional limited-cutline CD technique may not be sufficient to assure the identification of all lithographically marginal locations when designing a complicated photo-lithographic process.
Hence, what is needed is a MEEF analysis technique that overcomes the problems listed above.